The design of chiplet-based heterogeneous processing architectures is a complex systems engineering problem. A modern AI accelerator may integrate dozens of chiplets — specialized compute and memory dies — in a single package, with design decisions spanning chiplet micro-architecture (process node, array size, memory configuration) and package architecture (interconnect topology, number of hub and leaf chiplets). The space of possible designs is enormous, and evaluating any single design requires running detailed hardware simulators. This makes manual exploration of the design space impractical and motivates the use of AI-assisted methods.
This project, funded by the Lockheed Martin Corporate E&T/CTO University Research Program, develops an AI-assisted design space exploration (DSE) platform for chiplet-based heterogeneous processing architectures. The platform takes as input a set of high-level functional and performance requirements and a set of objectives to optimize, and identifies designs that meet all requirements while optimizing those objectives. The work is a collaboration between Texas A&M University (PI: Dr. Daniel Selva) and Harvard University (Co-PI: Dr. David Brooks).
The tool follows a micro-service architecture, with four core services: Problem Formulation, Design Evaluation, Design Synthesis/Optimization, and Design Analytics. All services are accessible through a web-based front end and coordinated by a central “Brain” running on AWS. An AI agent with a natural language interface allows the user to interact with all services seamlessly, from formulating the problem to interrogating the results.
In addition to answering questions, the tool can also control the different services mentioned above to perform tasks such as starting an optimization or data mining process, or comparing the results of two DSE runs.
Next Steps
Ongoing work focuses on: implementing a transformer-based generative design agent; extending the sub-agent architecture to support autonomous end-to-end DSE runs; and demonstrating the platform in a representative chiplet design case study for Lockheed Martin.
Funding
Lockheed Martin Corporate E&T/CTO University Research Program, 2024–2026.